Recently, an integration scale of semiconductor storage devices has been progressed and semiconductor storage devices using wiring width of 30 nm or less has been realized. If this trend continues, the wiring width of the semiconductor storage device will be in the order of 10 nm in a few years, and a new structure, material or process for further scaling down will be required.
With a conventional non-volatile semiconductor storage device using an oxide film for an insulation layer of a memory cell, if scaling down further proceeds, there is a concern that the insulation property of the oxide film does not function sufficiently. Hence, a trial has been made to reduce the size of a memory cell by, for example, using organic molecules in the memory cell.
Further, for example, lithography using the self-assembly phenomenon is proposed to realize ultrafine lithography at low cost.